82598EB Datasheet, PDF (149/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Wake Up
t_l2pg
t_l2clk
c_lkpg
t_pgdl
L2 link transition to PWRGD
de-assertion
0 ns
L2 link transition to removal
of PCIe reference clock
100 ns
PWRGD de-assertion to
removal of PCIe reference
clock
0 ns
PWRGD de-assertion time
100 s
According to PCIe specification.
According to PCIe specification.
According to PCIe specification.
According to PCIe specification.
3.3.1.5.5 Timing Guarantees
The 82598 guarantees the following start-up and power-state transition related timing parameters.
Table 3-43. Start-up and Power-State Transition Related Timing Parameters
Parameter
t_xog
t_ppg
t_ee
t_ppg-clkint
t_clkpr
t_pgtrn
t_pgres
Description
Min
Xosc stable from power stable
Internal power good delay from
valid power rail
35 ms
EEPROM read duration
PCIe PWRGD to internal PLL lock
-
Internal PCIe PWGD from external
PCIe PWRGD
PCIe PWRGD to start of link
training
External PWRGD to response to
first configuration cycle
Max.
10 ms
35 ms
Notes
20 ms
50 s
50 s
20 ms
According to PCIe specification.
1s
According to PCIe specification.
3.3.2 Wake Up
3.3.2.1 Advanced Power Management Wake Up
Advanced Power Management Wake Up, or APM Wake Up, was previously known as Wake on LAN
(WoL). It is a feature that has existed in the 10/100 Mb/s NICs for several generations. The basic
premise is to receive a broadcast or unicast packet with an explicit data pattern, and then to assert a
signal to wake up the system. In the earlier generations, this was accomplished by using a special
signal that ran across a cable to a defined connector on the motherboard. The NIC asserts the signal for
approximately 50 ms to signal a wake up. The 82598 uses (if configured to) an in-band PM_PME
message for this.
At power-up, the 82598 reads the APM Enable bit from the EEPROM into the APM Enable (APME) bits of
the GRC register This bit controls the enabling of APM wake up.
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