82598EB Datasheet, PDF (79/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
HwInit
RsvdP
RsvdZ
Hardware initialized. Register bits are initialized by firmware or hardware mechanisms such as pin strapping or
serial EEPROM. Bits are read-only after initialization and can only be reset (for write-once by firmware) with the
PWRGOOD signal.
Reserved and preserved. Reserved for future read-write implementations; software must preserve value read for
writes to these bits.
Reserved and zero. Reserved for future R/W1C implementations; software must use 0b for writes to these bits.
Table 3-13. PCI-Compatible Configuration Registers
Byte Offset
0x0
0x4
0x8
0xC
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
Byte 3
Byte 2
Byte 1
Byte 0
Device ID
Vendor ID (0x8086)
Status Register (0x0010)
Command Register (0x0000)
Class Code (0x020000, 0x010185, 0x070002, 0x0C0701)
Revision ID (0x03)
Reserved (0x00)
Header Type (0x00 |
0x80)
Latency Timer (0x00)
Cache Line Size (0x10)
Base Address 0
Base Address 1
Base Address 2
Base Address 3
Base Address 4
Base Address 5
Cardbus CIS Pointer (0x00000000)
Subsystem ID (0x0000)
Subsystem Vendor ID (0x8086)
Expansion ROM Base Address
Reserved (0x000000)
Cap_Ptr (0x40)
Reserved (0x00000000)
Max_Latency (0x00)
Min_Grant
(0x00)
Interrupt Pin
(0x01)
Interrupt Line
(0x00)
Interpretation of the various registers in the 82598 are described in the sections that follow.
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