82598EB Datasheet, PDF (134/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Software Initialization and Diagnostics
2. Configure the Speed Configuration field to 10 Gb/s or 1 Gb/s link in the AUTOC register (for KX4/KX
accordingly).
3. If necessary, configure any interface fields in the SERDESC register.
4. Configure the KX/KX4 Auto Negotiation Enable field to disabled in the AUTOC register. This causes
the Speed Control field to control the link.
5. Restart the link using the Restart Auto Negotiation field in the AUTOC register.
6. Check the link status (sync, align, link_up, speed) using the LINKS register.
The 82598 KX/KX4 with auto negotiation initialization is done using the following steps:
1. KX / KX4 link electrical setup is done according to EEPROM configuration to set the analog interface
to the appropriate setting.
2. If necessary, configure any interface fields in the SERDESC register.
3. Configure the KX/KX4 Auto Negotiation Enable field to enabled in the AUTOC register.
4. Configure the KX_Support field and any other auto negotiation related fields in the AUTOC register.
5. Restart the link using the Restart Auto Negotiation field in the AUTOC register.
6. Check the link status (sync, align, link_up, speed) using the LINKS register.
3.2.3.2.4 Initialization of Statistics
Statistics registers are hardware-initialized to values as detailed in each particular register's
description. The initialization of these registers begins upon transition to D0active power state (when
internal registers become accessible, as enabled by setting the Memory Access Enable field in the PCIe
Command register).
All of the statistical counters are cleared on read and a typical software device driver reads them (thus
making them zero) as a part of the initialization sequence.
3.2.3.2.5 Receive Initialization
Program the Receive Address Low – RAL (0x05400 + 8*n[n=0..15]; RW) and Receive Address High –
RAH (0x05404 + 8*n[n=0..15]; RW) registers with adapter addresses. If an EEPROM is present, RAL0
and RAH0 are loaded from it.
Set up the Multicast Table Array – MTA (0x05200-0x053FC; RW) if reception of Multicast packets is
required. The entire table should be zeroed and only desired multicast addresses should be permitted
(by writing 0x1 to corresponding bit location). The MFE bit should be set in order for multicast filtering
to take effect.
Set up the VLAN Filter Table Array – VFTA (0x0A000-0x0A9FC; RW) if VLAN support is required. The
entire table should be zeroed and only desired VLAN addresses should be permitted (by writing 0x1 to
corresponding bit location). The VFE bit should be set in order for VLAN Filtering to take effect.
Working with legacy interrupts:
Program the interrupt mask register to pass any interrupt the software device driver cares about. There
is no reason to enable the transmit interrupts.
If software uses the Receive Descriptor Minimum Threshold Interrupt, the RDMTS field of RDRXCTL
register should be set.
Program the Interrupt Vector allocation table.
Working with MSI-X:
Program the MSI-X table.
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