82598EB Datasheet, PDF (142/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Delivery
Two configuration bits are provided for the handshake between the device function and its software
device driver:
• GIO Master Disable bit in the Device Control (CTRL) register – When the GIO Master Disable bit is
set, the 82598 blocks new master requests by this function. The 82598 then proceeds to issue
any pending requests by this function. This bit is cleared on master reset (Internal Power On
Reset all the way to software reset) to enable master accesses.
• GIO Master Enable Status bits in the Device Status register – Cleared by the 82598 when the GIO
Master Disable bit is set and no master requests are pending by the relevant function. Set
otherwise. Indicates that no master requests are issued by this function as long as the GIO
Master Disable bit is set. The following activities must end before the 82598 clears the GIO
Master Enable Status bit:
• Master requests by the transmit and receive engines
• All pending completions to the 82598 are received.
Notes:
• The software device driver sets the GIO Master Disable bit when notified of a pending master
disable (or D3 entry). The 82598 then blocks new requests and proceeds to issue any pending
requests by this function. The software device driver then polls the GIO Master Enable Status bit.
Once the bit is cleared, it is guaranteed that no requests are pending from this function. The
software device driver might time out if the GIO Master Enable Status bit is not cleared within a
given time.
• The GIO Master Disable bit must be cleared to enable master request to the PCIe link. Can be
done either through reset or by the software device driver.
3.3.1.4.4 Dr State
Transition to Dr state is initiated on several occasions:
• On system power up – Dr state begins with the assertion of Internal Power On Reset or
LAN_PWR_GOOD and ends with de-assertion of PE_RST_N.
• On transition from a D0a state – During operation, the system might assert PE_RST_N at any
time. In an ACPI system, a system transition to the G2/S5 state causes a transition from D0a to
Dr state.
• On transition from a D3 state – The system transitions the 82598 into the Dr state by asserting
PCIe PE_RST_N.
Any wake-up filter settings that were enabled before entering this reset state are maintained.
The system might maintain PE_RST_N asserted for an arbitrary time. The de-assertion (rising edge) of
PE_RST_N causes a transition to D0u state.
While in Dr state, the 82598 might maintain functionality (for WoL or manageability) or might enter a
Dr Disable state (if no WoL and no manageability) for minimal 82598 power.
3.3.1.4.4.1 Dr Disable Mode
The 82598 enters a Dr Disable mode on transition to D3cold state when it does not need to maintain
any functionality. The conditions to enter either state are:
• The 82598 (all PCI functions) is in Dr state
• APM WOL is inactive for both LAN functions
• Pass-through manageability is disabled
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