82598EB Datasheet, PDF (348/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Field
Reserved
Reserved
ENDBUBD
Reserved
Bit(s)
Initial
Value
Description
0
0b
Reserved
1
0b
Reserved
2
0b
Enable DBU buffer division, enable writing to DBU non-zero buffer.
31:3
0x0
Reserved
4.4.3.7.10 Tx DCA Control Register – DCA_TXCTRL (0x07200 – 0x0723C; RW)
Field
CPUID
TX Descriptor DCA
EN
Reserved
TXdescRDNSen
TXdescRDROEn
TXdescWBNSen
TXdescWBROEn
TXDataReadNSEn
Bit(s)
4:0
5
7:6
8
9
10
11
12
Initial
Value
Description
0x0
Physical ID
In FSB platforms, the software device driver, upon discovery of the physical
CPU ID and CPU Bus ID, programs it into these bits for hardware to associate
Physical CPU and Bus ID with the adequate Tx Queue. Bits 2:1 are Target
Agent ID, bit 3 is the Bus ID. Bits 2:0 are copied into bits 3:1 in the TAG field
of the TLP headers of PCIe messages.
In CSI platforms, the software device driver programs a value, based on the
relevant APIC ID, corresponding to the adequate Tx queue. This value is going
to be copied in the 4:0 bits of the DCA Preferences field in TLP headers of
PCIe messages.
0b
Descriptor DCA EN
When set, hardware enables DCA for all Tx descriptors written back into
memory. When cleared, hardware does not enable DCA for descriptor write
backs. Default cleared.
Applies also to head write-back when enabled.
00b
Reserved
0b
Tx Descriptor Read No-Snoop Enable
Note: This bit must be reset to 0b to ensure correct functionality (except if
the software device driver has written this bit with write-through instruction).
1b
Tx Descriptor Read Relax Order Enable
0b
Tx Descriptor Write Back No-Snoop Enable
Note: This bit must be reset to 0b to ensure correct functionality of descriptor
write-back.
Applies also to head write-back when enabled.
1b
Tx Descriptor Write Back Relaxed Order Enable
Applies also to head write-back when enabled.
0b
Tx Data Read No-Snoop Enable
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