82598EB Datasheet, PDF (324/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
TXOFF0
TXOFF1
TXOFF2
TXOFF3
TXOFF4
TXOFF5
TXOFF6
TXOFF7
Reserved
8
0b
9
0b
10
0b
11
0b
12
0b
13
0b
14
0b
15
0b
31:16
0x0
Packet Buffer 0 Transmission Paused
Pause state indication of the PB0 when class-based flow control is enabled.
Packet Buffer 1 Transmission Paused
Pause state indication of the PB1 when class-based flow control is enabled.
Packet Buffer 2 Transmission Paused
Pause state indication of the PB2 when class-based flow control is enabled.
Packet Buffer 3 Transmission Paused
Pause state indication of the PB3 when class-based flow control is enabled.
Packet Buffer 4 Transmission Paused
Pause state indication of the PB4 when class-based flow control is enabled.
Packet Buffer 5 Transmission Paused
Pause state indication of the PB5 when class-based flow control is enabled.
Packet Buffer 6 Transmission Paused
Pause state indication of the PB6 when class-based flow control is enabled.
Packet Buffer 7 Transmission Paused
Pause state indication of the PB7 when class-based flow control is enabled.
Reserved
4.4.3.5 Receive DMA Registers
4.4.3.5.1 Receive Descriptor Base Address Low – RDBAL (0x01000 +
0x40*n[n=0..63]; RW)
Field
0
RDBAL
Bit(s)
Initial
Value
6:0
0x0
31:7
X
Description
Ignored on writes. Returns 0x0 on reads.
Receive Descriptor Base Address Low
This register contains the lower bits of the 64-bit descriptor base address. The lower seven bits are
ignored. The receive descriptor base address must point to a 16-byte aligned block of data.
4.4.3.5.2 Receive Descriptor Base Address High – RDBAH (0x01004 +
0x40*n[n=0..63]; RW)
Field
RDBAH
Bit(s)
Initial
Value
31:0
X
Description
Receive Descriptor Base Address [63:32]
324