82598EB Datasheet, PDF (177/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Hardware EEPROM Sections
3.4.3.3.7 PCIe Control – Offset 6 – LAN Power Consumption
Bit
15:8
7:5
4:0
Name
LAN D0 Power
Function 0
Common Power
LAN D3 Power
Default
0x0
0x0
0x0
Description
The value in this field is reflected in the PCI Power Management Data register of
the LAN functions for D0 power consumption and dissipation (Data_Select = 0
or 4). Power is defined in 100 mW units. The power includes also the external
logic required for the LAN function.
The value in this field is reflected in the PCI Power Management Data register of
function 0 when the Data_Select field is set to 8 (common function). The MSBs
in the Data register that reflects the power values are padded with zeros.
When one port is used, this field should be set to 0b.
The value in this field is reflected in the PCI Power Management Data register of
the LAN functions for D3 power consumption and dissipation (Data_Select = 3
or 7). Power is defined in 100 mW units. The power includes also the external
logic required for the LAN function. The MSBs in the Data register that reflects
the power values are padded with zeros.
3.4.3.3.8 PCIe Control – Offset 7
Bit
15:11
10:8
Name
Reserved
Flash Size
7
Reserved
6:2
Go Electrical Idle
Delay
1
Load Subsystem
IDs
0
Load Device ID
Default
0x0
000b
0b
0b
1b
1b
Description
Reserved.
Indicates Flash Size
000b = 64 kB.
001b = 128 kB.
010b = 256 kB.
011b = 512 kB.
100b = 1 MB.
101b = 2 MB.
110b = 4 MB.
111b = 8 MB.
The Flash size impacts the requested memory space for the Flash and
expansion ROM BARs in PCIe configuration space.
Reserved.
Permits a tune delay between the electrical idle symbol sent on the physical
lane and the go-electrical idle command to GIO-ana.
When set to 1b, indicates that the function is to load its PCIe sub-system ID
and sub-system vendor ID from the EEPROM (offset 0x8 and 0x9 in this
section).
When set to 1b, indicates that the function is to load its PCI device ID from
the EEPROM (offset 10 in this section and offset 2 in PCIe configuration space
0/1 section).
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