82598EB Datasheet, PDF (139/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Delivery
Figure 3-14. Link Power Management State Diagram
While in L0 state, the 82598 transitions the transmit lane(s) into L0s state once the idle conditions are
met for a period of time defined below.
L0s configuration fields are:
• L0s enable – The default value of the Active State Link PM Control field in the PCIe Link Control
register is set to 00b (both L0s and L1 disabled). System software might later write a different
value into the Link Control register. The default value is loaded on any reset of the PCI
configuration registers.
• The L0S_ENTRY_LAT bit in the PCIe Control (GCR) register, determines l0s entry latency. When
set to 0b, L0s entry latency is the same as L0s exit latency of the 82598 at the other end of the
link. When set to 1b, L0s entry latency is (L0s exit latency of the 82598 at the other end of the
link/4). The default value is 0b (entry latency is the same as L0s exit latency of the 82598 at the
other end of the link).
• L0s exit latency (as published in the L0s Exit Latency field of the Link Capabilities register) is
loaded from EEPROM. Separate values are loaded when the 82598 shares the same reference
PCIe clock with its partner across the link and when the 82598 uses a different reference clock
than its partner across the link. The 82598 reports whether it uses the slot clock configuration
through the PCIe Slot Clock Configuration bit loaded from the Slot_Clock_Cfg EEPROM bit.
• L0s Acceptable Latency (as published in the Endpoint L0s Acceptable Latency field of the Device
Capabilities register) is loaded from EEPROM.
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