82598EB Datasheet, PDF (314/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
PBUR
DHER
TCP Timer
Reserved
28
0b
Set RX/TX packet buffer unrecoverable error interrupt.
29
0b
Set RX/TX descriptor handler error interrupt.
30
0b
Set corresponding EICR TCP timer interrupt condition.
31
0b
Reserved
Software uses this register to set an interrupt condition. Any bit written with a 1b sets the
corresponding bit in the Extended Interrupt Cause register (see Section 4.4.3.3.1) and clears the
relevant EITR register if GPIE.EIMEN is set. An immediate interrupt is then generated if a bit in this
register is set and the corresponding interrupt is enabled using the Extended Interrupt Mask Set/Read
register.
If GPIE.EIMEN is not set, then an interrupt generated by setting a bit in this register waits for EITR
expiration.
Note: Bits written with 0b are unchanged.
4.4.3.3.3 Extended Interrupt Mask Set/Read Register EIMS (0x00880, RWS)
Field
RTxQ
Reserved
LSC
Reserved
MNG
Reserved
GPI_SDP0
GPI_SDP1
GPI_SDP2
GPI_SDP3
PBUR
DHER
TCP Timer
Reserved
Bit(s)
15:0
19:16
20
21
22
23
24
25
26
27
28
29
30
31
Initial
Value
0x0
0x0
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Description
Mask bit for corresponding EICR RTxQ interrupt condition.
Reserved
Mask link status change interrupt.
Reserved
Mask manageability event interrupt.
Reserved
Mask general purpose interrupt on SDP0.
Mask general purpose interrupt on SDP1.
Mask general purpose interrupt on SDP2.
Mask general purpose interrupt on SDP3.
Mask RX/TX packet buffer unrecoverable error interrupt.
Mask RX/TX descriptor handler error interrupt.
Mask bit for corresponding EICR TCP timer interrupt condition.
Reserved
314