82598EB Datasheet, PDF (566/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - XAUI, KX/KX4, CX4 and BX Layout Recommendations
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Figure 8-4. No Vias Between High-Speed Traces
8.3.2.5 Reference Planes
Do not cross plane splits with the MAUI high-speed differential signals. This causes impedance
mismatches and negatively affects the return current paths for the board design and layout. Refer to
Figure 8-5.
Traces should not cross POWER or GND plane splits if at all possible. Traces should stay 6x the dielectric
height away from plane splits or voids. If traces must cross splits, capacitive coupling should be added.
Figure 8-5. Do Not Cross Plane Splits
Figure 8-6. Traces 6x Dielectric Splits
Keep Rx and Tx separate. This helps to minimize crosstalk effects since the TX and RX signals are NOT
synchronous. This is the more "natural" routing method and will occur without much user interference.
It is also recommended that the MAUI signals stay at least 6x dielectric height away from any POWER
or GND plane split. This improves impedance balance and return current paths.
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