82598EB Datasheet, PDF (90/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
31:3
0x000
RO
2:0
0x3
RO
Table Offset. Used as an offset from the address contained by one of the function’s Base
Address registers to point to the base of the MSI-X table. The lower three Table BIR bits are
masked off (set to 0b) by software to form a 32-bit Qword-aligned offset.
Note that this field is read only.
Table BIR. Indicates which one of a function’s Base Address registers, beginning at 0x10 in
the configuration space, is used to map the function’s MSI-X table into the memory space.
BIR value Base Address register:
0 = 0x10.
1 = 0x14.
2 = 0x18.
3 = 0x1C.
4 = 0x20.
5 = 0x 24.
6 = Reserved.
7 = Reserved.
For a 64-bit Base Address register; the table BIR indicates the lower Dword.
Hardwired to 0b.
Table 3-23. Table Offset
Bits
Default
R/W
31:3
0x0400
RO
2:0
0x3
RO
Description
PBA Offset. The offset from the address contained in one of the function Base Address
registers; points to the base of the MSI-X PBA. The lower three PBA BIR bits are masked off
(set to 0b) by software to form a 32-bit Qword-aligned offset.
The field is read only.
PBA BIR. Indicates which of a function’s Base Address registers, beginning at 0x10 in
configuration space, is used to map the function’s MSI-X PBA into memory space.
PBA BIR value definitions are identical to those for the MSI-X table BIR.
This field is read only and set to 0b.
Table 3-24. MSI-X Table Structure
Dword3
Vector Control
Vector Control
Vector Control
…
Vector Control
Dword2
Msg Data
Msg Data
Msg Data
…
Msg Data
Dword1
Msg Upper Addr
Msg Upper Addr
Msg Upper Addr
…
Msg Upper Addr
Dword0
Msg Addr
Msg Addr
Msg Addr
…
Msg Addr
Entry 0
Entry 1
Entry 2
…
Entry (N-1)
Base
Base + 1*16
Base + 2*16
Base + (N-1) *16
Note: In the 82598, N =16
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