82598EB Datasheet, PDF (285/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Programming Interface
4. Programming Interface
4.1
Address Regions
The 82598’s address space is mapped into four regions along with the PCI Base Address registers.
These regions are listed in Table 4-1.
Table 4-1. Address Regions
Addressable Content
Mapping Style
Region Size
Internal registers and memories
Direct memory mapped
128 kB
Flash (optional)
Direct memory-mapped
64-512 kB
Expansion ROM (optional)
Direct memory-mapped
64-512 kB
Internal registers and memories, Flash (optional)
I/O Window mapped
32 bytes
MSI-X (optional)
Direct Memory mapped
16 kB
Both the Flash and Expansion ROM Base Address registers map the same Flash memory. The internal
registers, memories and Flash are be accessed though I/O space by doing a level of indirection.
4.2
Memory-Mapped Access
4.2.1 Memory-Mapped Access to Internal Registers and Memories
Internal registers and memories are be accessed as direct memory-mapped offsets from the base
address register (BAR0 or BAR0/BAR1). See Section 4.4 for the appropriate offset for each internal
register.
4.2.2 Memory-Mapped Accesses to Flash
External Flash is accessed using direct memory-mapped offsets from the Flash base address register
(BAR1 or BAR2/BAR3). Flash is only accessible if enabled through the EEPROM Initialization Control
Word, and if the Flash Base Address register contains a valid (non-zero) base memory address. For
accesses, the offset from the Flash BAR corresponds to the offset into the Flash’s actual physical
memory space.
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