82598EB Datasheet, PDF (276/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Interrupts
Case B: Light load, interrupts immediately on packet receive
Note:
To ensure the interrupts rate is properly controlled by software and is not affected by EICR
reads, the EITR restarts counting for the next interrupt trigger right after the interrupt trigger
and does not wait for the interrupt to be cleared as it used to wait in previous devices.
3.5.4.3 Clearing Interrupt Causes
The 82598 has three methods available for to clear EICR bits: Autoclear, clear-on-write, and clear-on-
read.
Auto-Clear
In systems that support MSI-X, the interrupt vector enables the interrupt service routine to know the
interrupt cause without reading the EICR. With interrupt moderation active, software loads from
spurious interrupts is minimized. In this case, the software overhead of a I/O read or write can be
avoided by setting appropriate EICR bits to autoclear mode by setting the corresponding bits in the
Extended Interrupt Auto-Clear (EIAC) register.
When auto-clear is enabled for a interrupt cause, the EICR bit is set when a cause event occurs. When
the EITR counter reaches zero, the MSI-X message is sent on PCIe. Then the EICR bit is cleared and
enabled to be set by a new cause event. The vector in the MSI-X message signals software the cause of
the interrupt to be serviced.
It is possible that in the time after the EICR bit is cleared and the interrupt service routine services the
cause, for example checking the transmit and receive queues, that another cause event occurs that is
then serviced by this ISR call, yet the EICR bit remains set. This results in a spurious interrupt.
Software can detect this case if there are no entries that require service in the transmit and receive
queues, and exit knowing that the interrupt has been automatically cleared. The use of interrupt
moderations through the EITR register limits the extra software overhead that can be caused by these
spurious interrupts.
Write to Clear
The EICR register clears specific interrupt cause bits in the register after writing 1b to those bits. Any
bit that was written with a 0b remains unchanged.
Read to Clear
All bits in the EICR register are cleared on a read to EICR If GPIE.OCD is not set. If set, only the other
causes bits are cleared on read.
3.5.4.4 Dynamic Interrupt Moderation
There are some types of network traffic for which latency is a critical issue. For these types of traffic,
interrupt moderation hurts performance by increasing latency between when a packet is received by
hardware and when it is indicated to the host operating system. This traffic can be identified by the TCP
port value, in conjunction with control bits, size, and VLAN priority.
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