82598EB Datasheet, PDF (254/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Transmit Functionality
Figure 3-26. Transmit Descriptor Ring Structure
Shaded boxes in Figure 3-26 show descriptors that have been transmitted but not yet reclaimed by
software. Reclaiming involves freeing up buffers associated with the descriptors.
The transmit descriptor ring is described by the following registers:
• Transmit Descriptor Base Address (TDBA) register (31:0) – This register indicates the start
address of the descriptor ring buffer in the host memory; this 64-bit address is aligned on a 16-
byte boundary and is stored in two consecutive 32-bit registers. Hardware ignores the lower four
bits.
• Transmit Descriptor Length (TDLEN) register (31:0) – This register determines the number of
bytes allocated to the circular buffer. This value must be 0b modulo 128.
• Transmit Descriptor Head (TDH) register (31:0) – This register holds a value that is an offset from
the base and indicates the in-progress descriptor. There can be up to 32K-8 descriptors in the
circular buffer. Reading this register returns the value of head corresponding to descriptors
already loaded in the output FIFO.
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