82598EB Datasheet, PDF (311/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Field
Abort
Reserved
RDCNT
Bit(s)
Initial
Value
Description
31
0b
Abort
Writing a 1b to this bit aborts the current burst read operation. It is also self-cleared by the
Flash interface block when the Abort command executed.
30:25
0x0
Reserved
24:0
0x0
Read Counter
This counter holds the size of the Flash burst read in Dwords.
4.4.3.2.9 Flash Opcode Register – FLOP (0x01013C; RW)
This register enables the host or firmware to define the op-code used in order to erase a sector of the
Flash or erase the entire Flash. This register is reset only at power on or during Internal Power On Reset
or LAN_PWR_GOOD.
Note: Default values are applicable to Atmel* Serial Flash Memory devices.
Field
SERASE
DERASE
Reserved
Bit(s)
Initial
Value
Description
7:0
0x52
Flash Block Erase Instruction
The op-code for the Flash block erase instruction and is relevant only to Flash access by
manageability.
15:8
0x62
Flash Device Erase Instruction
The op-code for the Flash erase instruction.
31:16
0x0
Reserved
4.4.3.2.10 General Receive Control – GRC (0x10200; RW)
Field
MNG_EN
APME
Reserved
Bit(s)
Initial
Value
Description
0
1b¹
Manageability Enable
This read-only bit indicates whether or not manageability functionality is enabled.
1
0b¹
Advance Power Management Enable
If set to 1b, manageability wakeup is enabled. The 82598 sets the PME_Status bit in the
Power Management Control/Status Register (PMCSR), asserts GIO_WAKE_N when
manageability wakeup is enabled, and when it receives a matching magic packet. It is a
single read/write bit in a single register, but has two values depending on the function that
accesses the register.
31:2
0x0
Reserved
311