82598EB Datasheet, PDF (349/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
TXDataReadROEn
Reserved
13
1b
31:14
0x0
Tx Data Read Relax Order Enable
Reserved
4.4.3.7.11 Transmit IPG Control – TIPG (0x0CB00; RW)
This register controls the Inter Packet Gap (IPG) timer. IPGT specifies the extension to the IPG length
for back-to-back transmissions.
Field
IPGT
Reserved
Bit(s)
Initial
Value
Description
7:0
0x0
IPG Transmit Time
Measured in increments of 4-byte times.
Note: For values greater than zero, the 82598 might violate the flow control timing
specification (from XOFF packet received to stopping the transmit side).
31:8
0x0
Reserved
4.4.3.7.12 Transmit Packet Buffer Size – TXPBSIZE (0x0CC00 – 0x0CC1C; RW)
Field
Reserved
SIZE
Reserved
Bit(s)
Initial
Value
9:0
0x0
19:10
0x28/0
Description
Reserved
Transmit Packet Buffer Size
Default values:
0x28 (40 kB) for TXPBSIZE0.
0x0 (0 kB) for RXPBSIZE1-7.
Other than the default configuration of one packet buffer, the 82598 supports a
partitioned configuration.
Partitioned transmit equal:
0x28 (40 kB) for TXPBSIZE0-7.
31:20
0x0
Reserved
4.4.3.7.13 Manageability Transmit TC Mapping – MNGTXMAP (0x0CD10; RW)
Field
MAP
Reserved
Bit(s)
Initial
Value
2:0
0x0
31:3
0x0
Description
MAP value indicates the TC that the transmit Manageability traffic is routed to.
Reserved
349