82598EB Datasheet, PDF (317/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Field
RTxQ
Reserved
LSC
Reserved
MNG
Reserved
GPI_SDP0
GPI_SDP1
GPI_SDP2
GPI_SDP3
PBUR
DHER
TCP Timer
Reserved
Bit(s)
15:0
19:16
20
21
22
23
24
25
26
27
28
29
30
31
Initial
Value
0x0
0x0
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Description
Auto-mask bit for corresponding EICR RTxQ interrupt condition.
Reserved
Auto-mask link status change interrupt.
Reserved
Auto-mask manageability event interrupt.
Reserved
Auto-mask general purpose interrupt on SDP0.
Auto-mask general purpose interrupt on SDP1.
Auto-mask general purpose interrupt on SDP2.
Auto-mask general purpose interrupt on SDP3.
Auto-mask RX/TX packet buffer unrecoverable error interrupt.
Auto-mask RX/TX descriptor handler error interrupt.
Auto-mask bit for corresponding EICR TCP timer interrupt condition.
Reserved
4.4.3.3.7 Extended Interrupt Throttle Registers – EITR (0x00820 – 0x0086C,
RW)
Each ITR is responsible for an interrupt cause. The allocation of ITR to interrupt cause is through MSI-X
allocation registers.
Field
Interval
Counter
Bit(s)
Initial
Value
15:0
0x0
31:16
Start
Description
Minimum Inter-interrupt Interval
The interval is specified in 256 ns increments. Zero disables interrupt throttling
logic.
Down Counter
Loaded with interval value each time the associated interrupt is signaled.
Counts down to zero and stops. The associated interrupt is signaled each time
this counter is zero and an associated (via the Interrupt Select register) EICR
bit is set.
This counter can be directly written by software at any time to alter the
throttles performance.
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