82598EB Datasheet, PDF (125/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Up
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Link training starts after t_pgtrn from PE_RST_N de-assertion.
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A first PCIe configuration access might arrive after t_pgcfg from PE_RST_N de-assertion.
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A first PCI configuration response can be sent after t_pgres from PE_RST_N de-assertion.
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Writing a 1b to the Memory Access Enable bit in the PCI Command Register transitions the 82598 from D0u to D0
state.
3.2.1.2.1 Timing Requirements
The 82598 requires the following start-up and power state transitions.
Table 3-35. Start-Up and Power-State Transitions
Parameter
t_xog
t_PWRGD-CLK
t_PVPGL
T_pgcfg
Description
Base 156 clock stable from
power stable
PCIe clock valid to PCIe power
good
Power rails stable to PCIe
PWRGD active
External PWRGD signal to first
configuration cycle.
Min
Max.
10 ms
100 s
-
100 ms -
100 ms
Notes
According to PCIe spec
According to PCIe spec
According to PCIe spec
Note:
It is assumed that the external 156.25 clock source is stable after the power is applied; the
timing for that is part of t_xog.
3.2.1.2.2 Timing Guarantees
The 82598 guarantees the following start-up and power state transition related timing parameters.
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