82598EB Datasheet, PDF (229/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Receive Functionality
3.5.2.5 Receive UDP Fragmentation Checksum
The 82598 might provide Receive fragmented UDP checksum offload. The following setup should be
made to enable this mode:
• The RXCSUM.PCSD bit should be cleared. The Fragment Checksum and IP Identification fields are
mutually exclusive with the RSS hash. When the PCSD bit is cleared, the Fragment Checksum and
IP Identification are active, instead of RSS hash.
• The RXCSUM.IPPCSE bit should be set. This field enables the IP payload checksum enable that is
designed for the fragmented UDP checksum.
The following table lists the outcome descriptor fields for the following incoming packets types.
Table 3-57. Descriptor Fields for Incoming Packet Types
Incoming Packet Type
Non IPv4 packet
Non fragmented IPv4 packet
Fragmented IPv4, when not first
fragment
Fragmented IPv4 with protocol =
UDP, first fragment (UDP protocol
present)
Fragment Checksum
0b
Same as above
The unadjusted 1’s complement
checksum of the IP payload
Same as above
UDPV
0b
0b
0b
UDPCS/L4CS
0b/0b for UDP
0b/1b for TCP
for IPv6 not fragmented
packet
else 0b/0b
Depends on transport
header
UDP: 1b/1b
TCP: 0b/1b
1b/0b
1b if the UDP
header checksum
is valid (not 0b)
1b/0b
Note: When the software device driver computes the 16-bit 1’s complement sum on the incoming
packets of the UDP fragments, it should expect a value of 0xFFFF.
3.5.2.6 Receive Descriptor Fetching
The fetching algorithm attempts to make the best use of PCIe bandwidth by fetching a cache-line (or
more) descriptor with each burst. The following sections briefly describe the descriptor fetch algorithm
and the software control provided.
When the on-chip buffer is empty, a fetch happens as soon as any descriptors are made available (host
writes to the tail pointer). When the on-chip buffer is nearly empty (RXDCTL.PTHRESH), a prefetch is
performed each time enough valid descriptors (RXDCTL.HTHRESH) are available in host memory and no
other PCIe activity of greater priority is pending (descriptor fetches and write-backs or packet data
transfers).
When the number of descriptors in host memory is greater than the available on-chip descriptor
storage, the 82598 might elect to perform a fetch that is not a multiple of cache line size. The hardware
performs this non-aligned fetch if doing so results in the next descriptor fetch being aligned on a cache
line boundary. This enables the descriptor fetch mechanism to be most efficient in the cases where it
has fallen behind software.
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