82598EB Datasheet, PDF (87/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
0
EEP PCIe control offset
EEP PCIe control offset
EEP PCIe control offset 6
01b
6
6
1
EEP PCIe control offset
EEP PCIe control offset
0x00
01b
6
6
Note: For other Data_Select values the Data register output is reserved (0b).
3.1.1.14.5 MSI Configuration
This structure is required for PCIe devices. There are no changes to this structure from the initial values
of the configuration registers. Defaults are marked in parenthesis.
Color Notation:
• Dotted – Fields that are identical to all functions
• Light-blue – Read-only fields
• Magenta – Hardcoded
Table 3-19. Message Signaled Interrupt Configuration Registers
Byte Offset
0x50
0x54
0x58
0x5C
Byte 3
Byte 2
Byte 1
Byte 0
Message Control (0x0080)
Next Pointer
Capability ID (0x05)
Message Address
Message Upper Address
Reserved
Message Data
Capability ID – 1 Byte, Offset 0x50, (RO) – This field equals 0x05, indicating the linked list item as
being Message Signaled Interrupt registers.
Next Pointer – 1 Byte, Offset 0x51, (RO) – This field provides an offset to the next item in the
capability list. Its value of 0x60 points to the MSI-X capability.
Message Control – 2 Byte, Offset 0x52, (R/W) – These fields are listed in Table 3-20. Note that there
is a dedicated register per PCI function to separately enable MSI.
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