82598EB Datasheet, PDF (8/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Contents
5.4.4
5.4.5
5.4.3.2 Channel States .............................................................................................. 526
5.4.3.3 Discovery ..................................................................................................... 526
5.4.3.4 Configurations............................................................................................... 526
5.4.3.5 Pass-Through Traffic States ............................................................................ 528
5.4.3.6 Asynchronous Event Notifications..................................................................... 529
5.4.3.7 Querying Active Parameters ............................................................................ 529
Resets ......................................................................................................................... 529
Advanced Workflows...................................................................................................... 530
5.4.5.1 Multi-NC Arbitration ....................................................................................... 530
5.4.5.2 External Link Control...................................................................................... 531
5.4.5.3 Multiple Channels (Fail-Over) .......................................................................... 531
5.4.5.4 Statistics ...................................................................................................... 533
6. Mechanical Specification ......................................................................................................... 535
6.1 Package Information................................................................................................................... 535
7. Electrical Specifications ........................................................................................................... 537
7.1 Operating Conditions .................................................................................................................. 537
7.2 Absolute Maximum Ratings.......................................................................................................... 537
7.3 Recommended Operating Conditions............................................................................................. 538
7.4 Power Delivery........................................................................................................................... 538
7.4.1 Power Supply Specifications............................................................................................ 538
7.4.2 Power Supply Sequencing .............................................................................................. 540
7.4.3 Power Consumption....................................................................................................... 542
7.5 DC Specifications ....................................................................................................................... 544
7.5.1 Digital I/O .................................................................................................................... 544
7.5.2 Open Drain I/O ............................................................................................................. 545
7.5.3 NC-SI I/O .................................................................................................................... 545
7.6 Digital I/F AC Specifications ......................................................................................................... 547
7.6.1 Digital I/O AC Specification............................................................................................. 547
7.6.2 EEPROM AC Specifications .............................................................................................. 549
7.6.3 Flash AC Specification .................................................................................................... 550
7.6.4 SMBus AC Specification.................................................................................................. 553
7.6.5 NC-SI AC Specification................................................................................................... 554
7.6.6 Reset Signals................................................................................................................ 556
7.6.6.1 POR_BYPASS (External) ................................................................................. 557
7.6.7 PCIe DC/AC Specification ............................................................................................... 557
7.6.7.1 PCIe Specification (Receiver and Transmitter).................................................... 557
7.6.7.2 PCIe Specification (Input Clock)....................................................................... 557
7.6.8 Reference Clock Specification.......................................................................................... 557
8 Design Guidelines.................................................................................................................... 561
8.1 Connecting the PCIe interface ...................................................................................................... 561
8.1.1 Link Width Configuration ................................................................................................ 561
8.1.2 Polarity Inversion and Lane Reversal................................................................................ 561
8.1.3 PCIe Reference Clock..................................................................................................... 561
8.1.4 Bias Resistor ................................................................................................................ 562
8.1.5 Miscellaneous PCIe Signals ............................................................................................. 562
8.2 Connecting the MAUI Interfaces ................................................................................................... 562
8.3 MAUI Channels Lane Connections ................................................................................................. 562
8.3.1 Bias Resistor ................................................................................................................ 562
8.3.2 XAUI, KX/KX4, CX4 and BX Layout Recommendations........................................................ 562
8.3.2.1 Board Stack Up Example................................................................................. 562
8.3.2.2 Trace Geometries .......................................................................................... 563
8.3.2.3 Other High-Speed Signal Routing Practices........................................................ 564
8.3.2.4 Via Usage ..................................................................................................... 565
8.3.2.5 Reference Planes ........................................................................................... 566
8.3.2.6 Dielectric Weave Compensation ....................................................................... 567
8.3.2.7 Impedance Discontinuities .............................................................................. 567
8.3.2.8 Reducing Circuit Inductance ............................................................................ 567
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