82598EB Datasheet, PDF (315/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Reading this register reveals which bits have an interrupt mask set. An interrupt in EICR is enabled if its
mask bit is set to 1b and disabled if its mask bit is set to 0b. A PCI interrupt is generated each a bit in
this register is set and the corresponding interrupt occurs (subject to throttling). The occurrence of an
interrupt condition is reflected by having a bit set in the Extended Interrupt Cause Read register (see
Section 4.4.3.3.1).
An interrupt might be enabled by writing a 1b to the corresponding mask bit location (as defined in the
EICR register) in this register. Bits written with a 0b are unchanged. Thus, if software needs to disable
a particular interrupt condition (previously enabled), it must write to the Extended Interrupt Mask Clear
Register, rather than writing a 0b to a bit in this register.
4.4.3.3.4 Extended Interrupt Mask Clear Register EIMC (0x00888, WO)
Field
RTxQ
Reserved
LSC
Reserved
MNG
Reserved
GPI_SDP0
GPI_SDP1
GPI_SDP2
GPI_SDP3
PBUR
DHER
TCP Timer
Reserved
Bit(s)
15:0
19:16
20
21
22
23
24
25
26
27
28
29
30
31
Initial
Value
0x0
0x0
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Description
Mask bit for corresponding EICR RTxQ interrupt condition.
Reserved
Mask link status change interrupt.
Reserved
Mask manageability event interrupt.
Reserved
Mask general purpose interrupt on SDP0.
Mask general purpose interrupt on SDP1.
Mask general purpose interrupt on SDP2.
Mask general purpose interrupt on SDP3.
Mask RX/TX packet buffer unrecoverable error interrupt.
Mask RX/TX descriptor handler error interrupt.
Mask bit for corresponding EICR TCP timer interrupt condition.
Reserved
Software uses this register to disable an interrupt. Interrupts are presented to the bus interface only
when the mask bit is 1b and the cause bit is 1b. The status of the mask bit is reflected in the Extended
Interrupt Mask Set/Read register and the status of the cause bit is reflected in the Interrupt Cause Read
register (see Section 4.4.3.3.1).
Software blocks interrupts by clearing the corresponding mask bit. This is accomplished by writing a 1b
to the corresponding bit location (as defined in the EICR register). Bits written with 0b are unchanged.
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