82598EB Datasheet, PDF (273/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Interrupts
Extended Interrupt
Auto Clear
Extended Interrupt
Auto Mask
EIAC
EIAM
Enables bits in the EICR to be cleared automatically following MSI-X interrupt
without a read or write of the EICR.
Enables bits in the EIMS to be set and cleared automatically.
Extended Interrupt Cause Registers (EICR)
This register records the interrupt causes to provide to the software information on the interrupt
source.
The interrupt causes include:
1. The Rx and Tx queues, each queue can be mapped to one of the 16 interrupt cause bits (RTxQ)
available in this register, in non MSI-X mode this mapping is defined by the 82598 software device
driver and it uses the same mapping mechanism used in the MSI-X allocation registers (IVAR). See
Section 3.5.4.6 for more details on the mapping mechanism.
2. Indication for the TCP timer interrupt.
3. Other bits in this register are the legacy indication of interrupts as the SDP bits, management,
unrecoverable ECC errors and link status change. There is a specific Other Cause bit that is set if
one of these bits are set, this bit can be mapped to a specific MSI-X interrupt message.
In MSI-X mode the bits in this register can be configured to auto-clear when the MSI-X interrupt
message is sent, in order to minimize driver overhead, and when using MSI-X interrupt signaling. In
addition, software can configure the register not to be read-on clear beside Other Cause bits if the
GPIE.OCD bit is set. When set, only the other causes bits are clear on read – The only case where
software reads the EICR in this mode, is if the Other interrupt bit is set.
In systems that do not support MSI-X, reading the EICR register clears it's bits or writing 1b's clears the
corresponding bits in this register. Most systems have write buffers that minimizes overhead, but this
might require a read operation to guarantee that the write has been flushed from posted buffers.
Extended Interrupt Cause Set Register (EICS)
This registers enables triggering an immediate interrupt by software, By writing 1b to bits in EICS the
corresponding bits in EICS is set and the relevant EITR is reset (as if the counter was written to zero) if
GPIE.EIMEN bit is set. If GPIE.EIMEN bit is not set, than setting the bit does not cause an immediate
interrupt, but it waits for the EITR to expire. Used usually to rearm interrupts, software didn't have time
to handle in the current interrupt routine.
Extended Interrupt Mask Set and Read Register (EIMS)
Extended Interrupt Mask Clear Register (EIMC)
Interrupts appear on PCIe only if the interrupt cause bit is a 1b and the corresponding interrupt mask
bit is 1b. Software blocks asserting an interrupt by clearing the corresponding bit in the mask register.
The cause bit stores the interrupt event regardless of the state of the mask bit. Clear and set make this
register more thread safe by avoiding a read-modify-write operation on the mask register. The mask bit
is set for each bit written to a one in the set register and cleared for each bit written in the clear
register. Reading the set register (EIMS) returns the current mask register value.
Extended Interrupt Auto Clear Enable Register (EIAC)
Each bit in this register enables clearing of the corresponding bit in EICR following interrupt generation.
When a bit is set, the corresponding bit in EICR is automatically cleared following an interrupt.
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