82598EB Datasheet, PDF (145/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Delivery
Table 3-39. D0a to D3 and Back Without PE_RST_N
Note
1
2
3
4
5
6
7
Description
Writing 11b to the Power State field of the Power Management Control/Status Register (PMCSR) transitions
the 82598 to D3.
The system can keep the 82598 in D3 state for an arbitrary amount of time.
To exit D3 state the system writes 00b to the Power State field of the Power Management Control/Status
Register (PMCSR).
APM wake up or manageability can be enabled based on what is read in the EEPROM.
After reading the EEPROM, the LAN ports are enabled and the 82598 transitions to D0u state.
The system can delay an arbitrary time before enabling memory access.
Writing a 1b to the Memory Access Enable bit or to the I/O Access Enable bit in the PCI Command register
transitions the 82598 from D0u to D0 state.
3.3.1.5.2 Transition from D0a to D3 and Back with PE_RST_N
Figure 3-16. D0a to D3 and Back with PE_RST_N
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