82598EB Datasheet, PDF (113/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Non-Volatile Memory (EEPROM/Flash)
• The 82598 enables access to any location in the EEPROM via the EEPROM CSR registers.
3.1.3.1.3.2 EEPROM Protected Areas
The 82598 defines two protected areas in the EEPROM. The first area is words 0x00-0x0F these words
hold the basic configuration and the pointers to all other configuration sections. The second area is a
programmable size area located at the end of the EEPROM and targeted at protecting the appropriate
sections that should be blocked for changes.
3.1.3.1.3.3 Activating the Protection Mechanism
Following an 82598 initialization, it reads the Init Control word from the EEPROM. It then turns on the
protection mechanism if word 0x0h [7:6] contains a valid signature (equals 01b) and bit 4 in word 0x0
is set to 1b (enable protection). Once the protection mechanism is turned on, word 0x0 becomes write-
protected and the area that is defined by word 0x0 becomes hidden (for example, read/write
protected).
Although possible by configuration, it is prohibited that the software section in the EEPROM be included
as part of the EEPROM protected area.
3.1.3.1.3.4 Non Permitted Accesses to Protected Areas in the EEPROM
This section refers to EEPROM accesses via the EEC (bit banging) or EERD (parallel read access)
registers. Following a write access to the write protected areas in the EEPROM, the hardware responds
properly on the PCIe bus, but does not initiate any access to the EEPROM. Following a read access to
the hidden area in the EEPROM (as defined by word 0x0), the hardware does not access the EEPROM
and returns meaningless data to the host.
Using bit banging, the SPI EEPROM can be accessed in a burst mode. For example, providing an opcode
address and then reading or writing data for multiple bytes. The hardware inhibits an attempt to access
the protected EEPROM locations even in burst accesses.
Software should not access the EEPROM in a Burst Write mode starting in a non protected area and
continue to a protected one. In such a case, it is not guaranteed that the write access to any area ever
takes place.
3.1.3.1.4 EEPROM Recovery
The EEPROM contains fields that if programmed incorrectly might affect the functionality of 82598. The
impact can range from incorrectly setting a function like LED programming, disabling an entire feature
like no manageability or link disconnection, to the inability to access the 82598 via the regular PCIe
interface.
The 82598 implements a mechanism that enables a recovery from a faulty EEPROM no matter what the
impact is by using an SMBus message that instructs the firmware to invalidate the EEPROM.
This mechanism uses an SMBus message that the firmware is able to receive in all modes, no matter
what the content of the EEPROM is (even in diagnostic mode). After receiving this kind of message, the
firmware clears the signature of the EEPROM in word 0x0 bit 7/6 to 00b. Afterwards, the BIOS/
operating system initiates a reset to force an EEPROM auto-load process that fails and enables access
to the 82598.
Firmware is programmed to receive such a command only from a PCIe reset until one of the functions
changes it status from D0u to D0a. Once one of the functions switches to D0a, it can be safely assumed
that the 82598 is accessible to the host and there is no more need for this function. This reduces the
possibility of malicious software to use this command as a back door and limits the time the firmware
must be active in non-manageability mode.
The command is sent on a fixed SMBus address of 0xC8. The format of the command is SMBus Write
Data Byte as follows:
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