82598EB Datasheet, PDF (208/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Rx/Tx Functions
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NC-SI Out Buffer Strength
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NC-SI In Buffer Strength
0b = Value 0 should be configured to the NC-SI out buffer strength.
1b = Value 1 should be configured to the NC-SI out buffer strength
0b = Value 0 should be configured to the NC-SI in buffer strength.
1b = Value 1 should be configured to the NC-SI in buffer strength.
3.5
Rx/Tx Functions
3.5.1 Device Data/Control Flows
This section describes both the transmit and receive data flows for the 82598.
3.5.1.1 Transmit Data Flow
Tx data flow provides a high-level description of all data/control transformation steps needed for
sending Ethernet packets over the wire.
Step
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Description
The host creates a descriptor ring and configures one of the 82598’s transmit queues with the address location,
length, head, and tail pointers of the ring (one of 32 available Tx queues).
The host transmits a packet provided by the TCP/IP stack. This packet arrives in one or more data buffers.
The host initializes the descriptor(s) that point to the data buffer(s) and adds additional control parameters that
describe the needed hardware functionality. The host places that descriptor in the correct location in the
appropriate Tx ring.
The host updates the appropriate Queue Tail Pointer (TDT).
The 82598’s DMA senses a change of a specific TDT and as a result sends a PCIe request to fetch the
descriptor(s) from host memory.
The descriptor’s content is received in a PCIe read completion and is written to the appropriate location in the
descriptor queue.
The DMA fetches the next descriptor and processes its contents. As a result, the DMA sends PCIe requests to
fetch the packet data from system memory.
The packet data is being received from PCIe read completions and passes through the transmit DMA, which
performs all programmed data manipulations on the packet data on the fly. These can include various CPU
offloading tasks such as TSO offloading and checksum offloads.
While the packet is passing through the DMA, it is stored into the transmit FIFO.
After the entire packet is stored in the transmit FIFO, it is then forwarded to the transmit switch module.
The transmit switch arbitrates between host and management packets and eventually forwards the packet to
the MAC.
The MAC appends the L2 CRC to the packet and sends the packet over the wire using a pre-configured
interface.
When all the PCIe completions for a given packet are complete, the DMA updates the appropriate descriptor(s).
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