82598EB Datasheet, PDF (138/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Delivery
• If the Auxiliary (AUX) Power PM Enable bit of the PCIe Device Control register is set, the 82598
might consume higher power for any purpose (even if PME_En is not set).
• If the Auxiliary (AUX) Power PM Enable bit of the PCIe Device Control register is cleared, higher
power consumption is determined by the PCI-PM legacy PME_En bit of the Power Management
Control/Status register (PMCSR).
If the PCIE_Aux bit in the EEPROM is cleared, the 82598 consumed aux power in Dr state independent
of the setting of either the PME_En bit or the Auxiliary (AUX) Power PM Enable bit.
3.3.1.3 Interconnects Power Management
This section describes the power reduction techniques used by the 82598’s main interconnects.
3.3.1.3.1 PCIe Link Power Management
The PCIe link state follows the power management state of the 82598. Since the 82598 incorporates
multiple PCI functions, the device power management state is defined as the power management state
of the most awake function:
• If any function is in D0 state (either D0a or D0u), the PCIe link assumes the 82598 is in D0 state.
Else:
• If the functions are in D3 state, the PCIe link assumes the 82598 is in D3 state.
Else:
• The device is in Dr state (PE_RST_N is asserted to all functions).
The 82598 supports all PCIe power management link states other than L1 ASPM:
• L0 state is used in D0u and D0a states.
• The L0s state is used in D0a and D0u states each time the link conditions apply.
• The L1 state is used in the D3 state.
• The L2 state is used in the Dr state following a transition from a D3 state if PCI-PM PME is
enabled.
• The L3 state is used in the Dr state following power up, on transition from D0a and also if PME is
not enabled in other Dr transitions.
The 82598 support for Active State Link Power Management is reported via the PCIe Active State Link
PM Support register loaded from EEPROM.
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