82598EB Datasheet, PDF (364/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
This register counts the number of times frames were received when there were no available buffers in
the appropriate queue to store the frames or the queue was disabled. The packet is still received if
there is space in the FIFO and the Drop_En bit for the target queue is clear (0b).
This register only increments if receives are enabled and does not increment when flow control packets
are received.
4.4.3.9.30 Receive Undersize Count – RUC (0x040A4; R)
Field
RUC
Bit(s)
Initial
Value
Description
31:0
0x0
Number of receive undersize errors.
This register counts the number of received frames that passed address filtering, were less than
minimum size (64 bytes from <Destination Address> through <CRC>, inclusively), and had a valid
CRC. It only increments if receives are enabled.
4.4.3.9.31 Receive Fragment Count – RFC (0x040A8; R)
Field
RFC
Bit(s)
Initial
Value
Description
31:0
0x0
Number of receive fragment errors.
This register counts the number of received frames that pass address filtering, are less than minimum
size (64 bytes from <Destination Address> through <CRC>, inclusively), and have a bad CRC. This is
slightly different from the Receive Undersize Count register. The register only increments if receives are
enabled.
4.4.3.9.32 Receive Oversize Count – ROC (0x040AC; R)
Field
ROC
Bit(s)
Initial
Value
Description
31:0
0x0
Number of receive oversize errors.
This register counts the number of received frames that pass address filtering and are greater than
maximum size. An oversized packet is defined according to MHADD.MFS. See Section 4.4.3.9.21.
If receives are not enabled, the register does not increment. Lengths are based on bytes in the received
packet from <Destination Address> through <CRC>, inclusively.
364