82598EB Datasheet, PDF (91/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
Table 3-25. MSI-X PBA Structure
Pending bits 0 through 63
Qword0
Base
Note: In the 82598, N = 20. Therefore, only Qword0 is implemented.
Table 3-26. MSI-X Table Structure (Message Address Field)
Bits
31:2
Default
0x00
Type
R/W
1:0
0x00
R/W
Description
Message Address. System-specified message lower address.
For MSI-X messages, the contents of this field from an MSI-X table entry specifies the
lower portion of the Dword-aligned address (AD[31:02]) for the memory write
transaction. This field is read/write.
Message Address. For proper Dword alignment, software must always write zeroes to
these two bits; otherwise the result is undefined. The state of these bits after reset
must be 0b. These bits are permitted to be read-only or read/write.
Table 3-27. MSI-X Table Structure (Message Upper Address Field)
Bits
31: 0
Default
Type
0x00
R/W
Description
Message Upper Address. System-specified message upper address bits. If this field is
zero, Single Address Cycle (SAC) messages are used. If this field is non-zero, Dual
Address Cycle (DAC) messages are used. This field is read/write.
Table 3-28. MSI-X Table Structure (Message Data Field)
Bits
31:0
Default
0x00
Type
R/W
Description
Message Data. System-specified message data.
For MSI-X messages, the contents of this field from an MSI-X table entry specifies the
data driven on AD[31:0] during the memory write transaction’s data phase. This field is
read/write.
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