82598EB Datasheet, PDF (101/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
4
RW
0b
Enter Compliance. Software is permitted to force a link to enter compliance mode at
the speed indicated in the Target Link Speed field by setting this bit to 1b in both
components on a link and then initiating a hot reset on the link.
The default value of this field following a fundamental reset is 0b.
5
RW
Hardwired to
Hardware Autonomous Speed Disable. When set to 1b, this bit disables hardware from
0b
changing the link speed for reasons other than attempting to correct unreliable link
operation by reducing link speed.
If the 82598 does not implement the associated mechanism it is permitted to hardwire
this bit to 0b.
3.1.1.14.8 PCIe Extended Configuration Space
PCIe configuration space is located in a flat memory-mapped address space. PCIe extends the
configuration space beyond the 256 bytes available for PCI to 4096 bytes. The 82598 decodes an
additional four bits (bits 27:24) to provide the additional configuration space as shown. PCIe reserves
the remaining four bits (bits 31:28) for future expansion of the configuration space beyond 4096 bytes.
The configuration address for a PCIe device is computed using a PCI-compatible bus, device, and
function numbers as follows:
31
28
0000b
27
20
Bus #
19
15
Device #
14 12
Funct #
11
2
Register Address (offset)
10
00b
PCIe extended configuration space is allocated using a linked list of optional or required PCIe extended
capabilities following a format resembling PCI capability structures. The first PCIe extended capability is
located at offset 0x100 in the device configuration space. The first Dword of the capability structure
identifies the capability/version and points to the next capability.
The 82598 supports the following PCIe extended capabilities:
• Advanced Error Reporting Capability – offset 0x100
• Serial Number Capability – offset 0x140
3.1.1.14.8.1 Advanced Error Reporting Capability
The PCIe advanced error reporting capability is an optional extended capability to support advanced
error reporting. The tables that follow list the PCIe advanced error reporting extended capability
structure for PCIe devices.
Register
Offset
0x00
0x04
0x08
Field
Description
PCIe CAP ID
Uncorrectable Error
Status
Uncorrectable Error
Mask
PCIe Extended Capability ID.
Reports error status of individual uncorrectable error sources on a PCIe device.
Controls reporting of individual uncorrectable errors by device to the host bridge via
a PCIe error message.
101