82598EB Datasheet, PDF (89/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
Byte Offset
0x60
0x64
0x68
Byte 3
Byte 2
Message Control (0x0080)
Table Offset
PBA Offset
Byte 1
Next Pointer
Byte 0
Capability ID (0x11)
Table BIR
PBA BIR
Capability ID – 1 Byte, Offset 0x60, (RO) – This field equals 0x11 indicating that the linked list item as
being the MSI-X registers.
Next Pointer – 1 Byte, Offset 0x61, (RO) – This field provides an offset to the next capability item in
the capability list. Its value of 0xA0 points to PCIe capability.
Message Control – 2 Byte, Offset 0x62, (R/W) – These register fields are listed in Table 3-21.
Table 3-21. MSI-X Message Control Field
Bits
Default
R/W
10:0
0x013
RO
13:1
1
14
000b
0b
RO
R/W
15
0b
R/W
Description
Table Size. System software reads this field to determine the MSI-X Table Size N, which is
encoded as N-1. The 82598 supports up to 20 different interrupt vectors per function.
Always returns 000b on a read. A write operation has no effect.
Function Mask. If 1b, all of the vectors associated with the function are masked, regardless
of their per-vector Mask bit states.
If 0b, each vector’s Mask bit determines whether the vector is masked or not.
Setting or clearing the MSI-X Function Mask bit has no effect on the state of the per-vector
Mask bits.
MSI-X Enable. If 1b and the MSI Enable bit in the MSI Message Control register is 0b, the
function is permitted to use MSI-X to request service and is prohibited from using its INTx#
pin.
System configuration software sets this bit to enable MSI-X. A device driver is prohibited
from writing this bit to mask a function’s service request.
If 0b, the function is prohibited from using MSI-X to request service.
Table 3-22. MSI-X Table Offset
Bits
Default
R/W
Description
89