82598EB Datasheet, PDF (356/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Accessing the FHFT registers during filter operation might result in a packet being mis-classified if the
write operation collides with packet reception. Therefore, flex filters should be disabled prior to
changing their setup.
4.4.3.9 Statistic Registers
All statistics registers reset when read. In addition, they stick at 0xFFFF_FFFF when the maximum value
is reached.
For the receive statistics, note that a packet is indicated as received if it passes the 82598’s filters and
is placed into the packet buffer memory. A packet does not have to be transferred to host memory in
order to be counted as received.
Due to paths between interrupt-generation and logging of relevant statistics counts, it might be
possible to generate an interrupt to the system for an event prior to the associated statistics count
actually being incremented. This is unlikely due to expected delays associated with the system
interrupt-collection and ISR delay, but might be observed as an interrupt for which statistics values do
not quite make sense.
Hardware guarantees that any event noteworthy of inclusion in a statistics count is reflected in the
appropriate count within 1 μs; a small time-delay prior to reading the statistics might be necessary to
avoid the potential for receiving an interrupt and observing an inconsistent statistics count as part of
the ISR.
4.4.3.9.1 CRC Error Count – CRCERRS (0x04000; R)
Field
CRCERRS
Bit(s)
Initial
Value
31:0
0x0
CRC Error Count
Description
Counts the number of receive packets with CRC errors. In order for a packet to be counted in this
register, it must be 64 bytes or greater (from <Destination Address> through <CRC> inclusively) in
length. If receives are not enabled, then this register does not increment. This register counts all
packets received, not just packets that are directed to the 82598.
4.4.3.9.2 Illegal Byte Error Count – ILLERRC (0x04004; R)
Field
ILLERRC
Bit(s)
Initial
Value
31:0
0x0
Illegal Byte Error Count
Description
Counts the number of receive packets with illegal bytes errors (an illegal symbol in the packet). This
register counts all packets received, not just packets that are directed to the 82598.
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