82598EB Datasheet, PDF (5/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Contents
3.1.3 Non-Volatile Memory (EEPROM/Flash) .............................................................................. 111
3.1.3.1 EEPROM ....................................................................................................... 111
3.1.3.2 Flash............................................................................................................ 114
3.1.4 Network Interface ......................................................................................................... 116
3.1.4.1 10 GbE Interface ........................................................................................... 116
3.1.4.2 GbE Interface................................................................................................ 117
3.1.4.3 Auto Negotiation and Link Setup Features ......................................................... 117
3.1.4.4 MDIO/MDC ................................................................................................... 118
3.1.4.5 Ethernet (Legacy) Flow Control........................................................................ 119
3.1.4.6 MAC Speed Change at Different Power Modes .................................................... 121
3.2 Initialization .............................................................................................................................. 122
3.2.1 Power Up ..................................................................................................................... 122
3.2.1.1 Power-Up Sequence ....................................................................................... 122
3.2.1.2 Power-Up Timing Diagram .............................................................................. 124
3.2.1.3 Reset Operation ............................................................................................ 126
3.2.2 Specific Function Enable/Disable ..................................................................................... 129
3.2.2.1 General ........................................................................................................ 129
3.2.2.2 Overview ...................................................................................................... 129
3.2.2.3 Event Flow for Enable/Disable Functions ........................................................... 130
3.2.2.4 Device Disable Overview................................................................................. 131
3.2.3 Software Initialization and Diagnostics ............................................................................. 132
3.2.3.1 Power Up State ............................................................................................. 132
3.2.3.2 Initialization Sequence ................................................................................... 132
3.3 Power Management and Delivery.................................................................................................. 136
3.3.1 Power Delivery ............................................................................................................. 136
3.3.1.1 82598 Power States ....................................................................................... 137
3.3.1.2 Auxiliary Power Usage .................................................................................... 137
3.3.1.3 Interconnects Power Management.................................................................... 138
3.3.1.4 Power States................................................................................................. 140
3.3.1.5 Timing of Power-State Transitions.................................................................... 143
3.3.2 Wake Up ...................................................................................................................... 149
3.3.2.1 Advanced Power Management Wake Up ............................................................ 149
3.3.2.2 ACPI Power Management Wakeup .................................................................... 150
3.3.2.3 Wake-Up Packets........................................................................................... 151
3.4 NVM Map (EEPROM) ................................................................................................................... 157
3.4.1 EEPROM General Map .................................................................................................... 157
3.4.2 EEPROM Software Section .............................................................................................. 159
3.4.2.1 Compatibility Fields – Words 0x10-0x14 ........................................................... 159
3.4.2.2 PBA Number Module – Words 0x15:0x16 .......................................................... 159
3.4.2.3 Software EEGEN Work Area............................................................................. 160
3.4.2.4 PXE Configuration Words – Word 0x30:3B......................................................... 161
3.4.2.5 EEPROM Checksum Calculation ........................................................................ 165
3.4.3 Hardware EEPROM Sections............................................................................................ 166
3.4.3.1 EEPROM Init Section ...................................................................................... 166
3.4.3.2 EEPROM Hardware Pointers ............................................................................. 168
3.4.3.3 EEPROM PCIe General Configuration Section ..................................................... 171
3.4.3.4 EEPROM PCIe Configuration Space 0/1 Sections................................................. 178
3.4.3.5 EEPROM Core 0/1 Section ............................................................................... 179
3.4.3.6 EEPROM MAC 0/1 Sections .............................................................................. 182
3.4.4 Hardware Section – Auto-Read ....................................................................................... 187
3.4.5 Manageability Control Sections........................................................................................ 188
3.4.5.1 Common Firmware Pointers ............................................................................ 189
3.5 Rx/Tx Functions ......................................................................................................................... 208
3.5.1 Device Data/Control Flows.............................................................................................. 208
3.5.1.1 Transmit Data Flow ........................................................................................ 208
3.5.1.2 Rx Data Flow ................................................................................................ 209
3.5.2 Receive Functionality ..................................................................................................... 211
3.5.2.1 Packet Filtering ............................................................................................. 214
3.5.2.2 Intel® 82598 10 GbE Controller System Manageability Interface application
noteReceive Data Storage ............................................................................... 218
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