82598EB Datasheet, PDF (181/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Hardware EEPROM Sections
3.4.3.5.3 LEDs Configuration – Offset 4-5
The LEDCTL register defaults are loaded from these two words as listed in the following table:
LED
LED 0 Control
LED 1 Control
LED 2 Control
LED 3 Control
LEDCTL Bits
7:0
15:8
23:16
31:241
EPROM Byte
Word 0x4 (low byte).
Word 0x4 (high byte).
Word 0x5 (low byte).
Word 0x5 (high byte).
Note: The content of the EEPROM words is similar to the register content.
3.4.3.5.4 SDP Control – Offset 6
Bit
15:1
2
11
Name
Reserved
SDPDIR[3]
10
SDPDIR[2]
9
SDPDIR[1]
8
SDPDIR[0]
7:4
Reserved
3
SDPVAL[3]
Default
0000b
Should be set to 0000b.
Description
0b
SDP3 Pin – Initial Direction
Mapped to ESDP.SDP3_IODIR.
This bit configures the initial hardware value of the SDP3_IODIR bit in the ESDP
register following power up.
0b
SDP2 Pin – Initial Direction
Mapped to ESDP.SDP2_IODIR.
This bit configures the initial hardware value of the SDP2_IODIR bit in the ESDP
register following power up.
0b
SDP1 Pin – Initial Direction
Mapped to ESDP.SDP1_IODIR.
This bit configures the initial hardware value of the SDP1_IODIR bit in the ESDP
register following power up.
0b
SDP0 Pin – Initial Direction
Mapped to ESDP.SDP0_IODIR.
This bit configures the initial hardware value of the SDP0_IODIR bit in the ESDP
register following power up.
0x0
Reserved.
0b
SDP3 Pin – Initial Output Value
Mapped to ESDP.SDP3_DATA.
This bit configures the initial power on value output of SDP3 (when configured as an
output) by configuring the initial hardware value of the SDP3_DATA bit in the ESDP
register following power up.
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