82598EB Datasheet, PDF (316/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
This register provides software with a way to disable interrupts. Software disables a given interrupt by
writing a 1b to the corresponding bit.
4.4.3.3.5 Extended Interrupt Auto Clear Register EIAC (0x00810, RW)
Field
RTxQ
Reserved
LSC
Reserved
MNG
Reserved
GPI_SDP0
GPI_SDP1
GPI_SDP2
GPI_SDP3
PBUR
DHER
TCP Timer
Reserved
Bit(s)
15:0
19:16
20
21
22
23
24
25
26
27
28
29
30
31
Initial
Value
0x0
0x0
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Description
Auto-clear bit for corresponding EICR RTxQ interrupt condition.
Reserved
Auto-clear link status change interrupt.
Reserved
Auto-clear manageability event interrupt
Reserved
Auto-clear general purpose interrupt on SDP0.
Auto-clear general purpose interrupt on SDP1.
Auto-clear general purpose interrupt on SDP2.
Auto-clear general purpose interrupt on SDP3.
Auto-clear RX/TX packet buffer unrecoverable error interrupt.
Auto-clear RX/TX descriptor handler error interrupt.
Auto-clear bit for corresponding EICR TCP timer interrupt condition.
Reserved
This register is mapped like previous interrupt registers; each bit is mapped to a corresponding bit in
the EICR. EICR bits that have auto-clear set are cleared when the MSI-X message that they trigger is
sent on the PCIe bus. Note that an MSI-X message might be delayed by ITR moderation (from the time
the EICR bit is activated). Bits without auto-clear set need to be cleared using a write-to-clear.
Read-to-clear is not compatible with auto-clear; if any bits are set to auto-clear, read-to-clear should be
disabled (use the configuration register bit).
Bits 29:20 should never be set to auto clear since they share the same MSI-X vector.
4.4.3.3.6 Extended Interrupt Auto Mask Enable Register – EIAM (0x00890, RW)
Each bit in this register enables the setting of the corresponding bit in the EIMC register following a
write-to-clear to the EICR register or the setting of the corresponding bit in the EIMS register following
a write-to-set to the EICS register.
316