82598EB Datasheet, PDF (272/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Interrupts
3.5.3.7 Transmit Completions Head Write Back
In legacy hardware, transmit requests are completed by writing the DD bit to the transmit descriptor
ring. This causes cache thrash since both the software device driver and hardware are writing to the
descriptor ring in host memory. Instead of writing the DD bits to signal that a transmit request is
complete, hardware can write the contents of the descriptor queue head to host memory. The software
device driver reads that memory location to determine which transmit requests are complete. To
improve the performance of this feature, the software device driver needs to program the DCA registers
to configure which CPU is processing each TX queue.
3.5.3.7.1 Description
The head counter is reflected in a memory location that is allocated by the software for each queue.
Head write-back occurs if TDWBAL#.Head_WB_En is set for this queue and the RS bit is set in the Tx
descriptor, following a corresponding data upload into packet buffer.
The software device driver has control on this feature through Tx queue 63:0 write-back address, low
and high (thus allowing 64-bit address).
The low register's LSB hold the control bits.
• The Head_WB_En bit enables activation of head write-back. In this case, no descriptor write-back
is executed.
• The upper 30 bits of this register hold the lowest 32 bits of the head write-back address,
assuming that the two last bits are zero.
The high register holds the high part of the 64-bit address.
The 82598 writes the 32 bits of the queue head register to the address pointed by the TDEWBAH/
TDWBAL registers.
3.5.4 Interrupts
3.5.4.1 Registers
The interrupt logic consists of the registers listed in the following table, plus the registers associated
with MSI/MSI-X signaling.
Register
Extended Interrupt
Cause
Extended Interrupt
Cause Set
Extended Interrupt
Mask Set/Read
Extended Interrupt
Mask Clear
Acronym
EICR
EICS
Function
Extended ICR. Records all interrupt causes – an interrupt is signaled when
unmasked bits in this register are set.
Enables software to set bits in the Extended Interrupt Cause register.
EIMS
Sets or read bits in the extended interrupt mask.
EIMC
Clears bits in the extended interrupt mask.
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