82598EB Datasheet, PDF (119/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Network Interface
3.1.4.5 Ethernet (Legacy) Flow Control
Flow control as defined in 802.3x, as well as the specific operation of asymmetrical flow control defined
by 802.3z, is supported by the 82598. The following four registers are defined for the implementation
of flow control:
• Flow Control Receive Thresh High (FCRTH0) – 13-bit high water mark indicating receive buffer
fullness
• Flow Control Receive Thresh Low (FCRTL0) – 13-bit low water mark indicating receive buffer
emptiness
• Flow Control Transmit Timer Value (FCTTV0) – 16-bit timer value to include in transmitted pause
frame
• Flow Control Refresh Threshold Value (FCRTV0) – 16-bit pause refresh threshold value
Flow control is implemented as a means of reducing the possibility of receive buffer overflows, which
result in the dropping of received packets, and allows for local controlling of network congestion levels.
This might be accomplished by sending an indication to a transmitting station of a nearly full receive
buffer condition at a receiving station.
The implementation of asymmetric flow control allows for one link partner to send flow control packets
while being allowed to ignore their reception. For example, not required to respond to pause frames.
3.1.4.5.1 MAC Control Frames and Reception of Flow Control Packets
Three comparisons are used to determine the validity of a flow control frame:
1. A match on the six byte multicast address for MAC control frames or to the station address of the
device (Receive Address Register 0).
2. A match on the type field.
3. A comparison of the MAC Control Opcode field.
The 802.3x standard defines the MAC control frame multicast address as 01-80-C2-00-00-01.
A value of 0x8808 is compared against the flow control packet's type field to determine if it is a valid
flow control packet: XON or XOFF.
The final check for a valid pause frame is the MAC control opcode. At this time only the pause control
frame opcode is defined. It has a value of 0x0001.
Frame-based flow control differentiates XOFF from XON based on the value of the Pause Timer field.
Non-zero values constitute XOFF frames while a value of zero constitutes an XON frame. Values in the
timer field are in units of slot time. A slot time is hard wired to 64 byte times, or 512 ns.
XON frame signals the cancellation of the pause from initiated by an XOFF frame. Pause for zero slot
times.
The receiver is enabled to receive flow control frames if flow control is enabled via the RFCE bit in the
FCTRL Register.
Flow control capability must be negotiated between link partners via the auto negotiation process. It is
the driver responsibility to reconfigure the flow control configuration after the auto negotiation process
was resolved as it might modify the value of these bits based on the resolved capability between the
local device and the link partner.
Once the receiver has validated the reception of an XOFF, or PAUSE frame, the device performs the
following:
• Increment the appropriate statistics register(s)
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