82598EB Datasheet, PDF (233/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Receive Functionality
Figure 3-24. Header Splitting with Replicated Header
The physical address of each buffer is written in the Buffer Addresses fields:
• The packet buffer address includes the address of the buffer assigned to the replicated packet,
including header and data payload portions of the received packet. In case of split header, only
the payload is included.
• The header buffer address includes the address of the buffer that contains the header
information. The receive DMA module stores the header portion of the received packets into this
buffer.
The sizes of these buffers are statically defined in the SRRCTL[n] registers:
• The BSIZEPACKET field defines the size of the buffer for the received packet.
• The BSIZEHEADER field defines the size of the buffer for the received header. If header split or
header replication are enabled, this field must be configured to a non-zero value. The amount of
data written into the header buffer is different in header split and header replication modes:
—Header split – the 82598 only writes the header portion into the header buffer. The header size
is determined by the options enabled in the PSRTYPE registers.
—Header replication – the 82598 writes beyond the header up to the full size of the header buffer
(or to the size of the packet, if smaller).
The 82598 uses the packet replication or splitting feature when the SRRCTL[n].DESCTYPE > one.
When header split or header replication is selected, the packet is split (or replicated) only on selected
types of packets. A bit exists for each option in PSRTYPE[n] registers, so several options can be used in
conjunction. If one or more bits are set, the splitting (or replication) is performed for the corresponding
packet type. See Section 3.5.2.4 for details on the possible headers type supported.
The following table lists the behavior of the 82598 in the different modes:
233