82598EB Datasheet, PDF (3/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Revisions
Revisions
Rev
2.0
Date
12/08
2.2
February
2008
2.3
May 2008
2.4
August 2008
2.5
November
2008
3.1
April 2009
3.2
3.21
3.22
3.23
October 24,
2010
December 9,
2010
December 15,
2011
September
2012
Comments
• Converted to single source using FrameMaker.
• Updated internal/external pull-up/pull-down information.
Initial Release (Intel Public).
Updated sections/figures/tables: Product Features, 1.9.9, 2.2, 2.3, 2.9, 2.13, Table 2-17,
3.1.1.6, Table 3-17, 3.1.1.14.4, Note after Table 3-25, Device Cap, Device Control,
Device Status, Link CAP Lin Control, Link Status, tables in section 3.1.1.14.6, 3.1.3.1,
Figure 3-10, 3.2.1.2, 3.2.1.3, Table 3-38, Table 3-39, 3.2.3.2.5, Figure 3-12, Figure 3-
13, 3.3.2.3.1.7, Table 3-45, 3.4.3.1.1, 3.4.3.1.2, 3.4.3.4.2, 3.4.3.6.2, Figure 3-20,
Figure 3-21, Table 3-54, 3.5.2.4, 3.5.2.8, 3.5.2.10.1, 3.5.2.11, Table 3-59, Table 3-69,
3.5.3.3.2, 3.5.4.1, 3.5.4.2, Table 4-2, Table 4-4, 4.4.3.3.1 through 4.4.3.7, 4.4.3.3.12,
4.4.3.5.7 through 4.4.5.9, 4.4.3.6.2, 4.4.3.6.8, 4.4.3.6.11, 4.4.3.9, 4.4.3.11.1,
4.4.3.13.5, 4.4.3.13.8 through 4.4.3.13.10, 4.4.3.13.24, Table 5-7 through Table 5-10,
Table 5-12, and 5.6.4, 5.6.6.
Replaced Large Send Offload (LSO) with TCP Segmentation Offload (TSO).
Removed all references to “Header Replication”.
Updated reference schematics.
Updated Tables: 2-12, 2-14, 2-16, 3-17, 3-58, 3-71, 4-4, 5-3 through 5-5, 5-12, 5-15,
5-19,
Updated Section: 1.2, 1.8, 1.9.10, 2.13, 3.1.1.10.1, 3.1.1.14.2, 3.2.2.14.3.1,
3.1.1.14.4, 3.1.4.3.4, 3.2.1.3, 3.3.1.3.2, 3.3.1.4.1, 3.3.1.4.4.2, 3.4 through 3.4.4,
3.5.2, 4.4.3.1.1, 4.4.3.3.7, 4.4.3.5.7, 4.4.3.6.4, 4.4.3.9.49, 4.4.3.9.50, 5.4.3, 5.5.1,
7.6, 7.8, 7.13.2.
Updated Section: 3.2.1.2, 3.4.2.2.8, 3.4.2.3.2, 3.4.2.3.3, 3.4.2.5.2, 3.4.2.5.4, 3.4.3,
3.5.2.13, 3.5.3.2, 3.5.3.3.1.1, 3.5.3.3.1.3, 3.5.5.2, 3.5.5.3.1. 3.5.5.3.2, 3.5.6.1, 3.5.7,
4.4.3.1.6, 4.4.3.5.7, 4.4.3.6.13, 4.4.3.7.6, 4.4.3.9.5, 4.4.3.10.5, 4.4.3.10.6, 4.4.3.10.7,
4.4.3.10.8, 4.4.3.10.9, 4.4.3.13.8, 4.4.3.13.15, 4.4.3.13.23, 4.4.3.13.24, 4.4.3.13.25,
5.4.2, 5.5.1, 5.5.2, 5.6.6, and 5.6.6.1.
Updated Table 5-2, 5-6 and supported figure.
Updated Figure 5-1 notes.
Added Section 7.16.8.
Section 4.4.3.5.12, Drop Enable Control – DROPEN (0x03D04 – 0x03D08; RW) -
Description updated for clarity.
Section 5.3.13, Sample Configurations - Sample filtering configurations added.
Section 9.1.1, GHOST ECC Register - GHECCR (0x110B0, RW). Diagnostic register added
to public documentation because it has limited public use as a workaround.
Support for PCIe* Statistics Counters dropped.
Section 3.4.2.2, PBA Number Module – Words 0x15:0x16. Updated to reflect new
methodology.
Minor corrections.
Section 3.4.5.1.7.7, NC-SI Configuration (0ffset 0x06). Updated.
Section 3.4.3.2.1, Analog Configuration Sections – Words 0x04:0x05. Updated. In the
table, "configuration data" and "configuration addess" were swapped.
Section 3.4.3.2.1.2, EEPROM Analog Configuration – Data Word. Section content
updated. Now reads “Each word in the analog configuration section has the same
structure: bits 7:0 are the register data and bits 15:8 are the registers address. The
analog registers are eight bits wide with an 8-bit address width. After reading the
EEPROM word, the register specified in bits 15:8 is loaded with the data from bits 7:0.”
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