82598EB Datasheet, PDF (331/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.6 Receive Registers
4.4.3.6.1 Receive Checksum Control – RXCSUM (0x05000; RW)
Field
Reserved
IPPCSE
PCSD
Reserved
Bit(s)
Initial
Value
Description
11:0
0x0
Reserved
12
0b
IP Payload Checksum Enable
13
0b
RSS/Fragment Checksum Status Selection
When set to 1b, the extended descriptor write-back has the RSS field. When set to
0b, it contains the fragment checksum.
31:14
0x0
Reserved
The Receive Checksum Control register controls receive checksum offloading features. The 82598
supports offloading of three receive checksum calculations: the fragment checksum, the IP header
checksum, and the TCP/UDP checksum.
PCSD
The Fragment Checksum and IP Identification fields are mutually exclusive with the RSS hash. Only one
of the two options is reported in the Rx descriptor. The RXCSUM.PCSD affect is listed in the following
table:
RXCSUM.PCSD
0 (Checksum Enable)
Fragment checksum and IP identification are
reported in the Rx descriptor
1 (Checksum Disable)
RSS hash value is reported in the Rx descriptor
IPPCSE
This is the IPPCSE control the fragment checksum calculation. As previously noted, the fragment
checksum shares the same location as the RSS field. The fragment checksum is reported in the receive
descriptor when the RXCSUM.PCSD bit is cleared.
If RXCSUM.IPPCSE cleared (the default value), the checksum calculation is not done and the value that
is reported in the Rx fragment checksum field is 0b.
If the RXCSUM.IPPCSE is set, the fragment checksum is aimed to accelerate checksum calculation of
fragmented UDP packets.
This register should only be initialized (written) when the receiver is not enabled (only write this
register when RXCTRL.RXEN = 0b).
331