82598EB Datasheet, PDF (172/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Hardware EEPROM Sections
14:12
L1_Act_Ext_Latency
110b
11:9
L1_Act_Acc_Latency
110b
8:6
L0s_Acc_Latency
011b
L1 active exit latency for the configuration space
Default = (32 μs-64 μs).
Defined encoding:
000b = Less than 1 s.
001b = 1 s – 2 s.
010b = 2 s – 4 s.
011b = 4 s – 8 s.
100b = 8 s – 16 s.
101b = 16 s – 32 s.
110b = 32 s – 64 s.
111b = More than 64 s.
These bits configure the initial hardware value of the PCI configuration,
Link CAP, and L1 Exit Latency registers following power up.
L1 active acceptable latency for the configuration space
Default = (32 μs-64 μs).
Defined encoding:
000b = Less than 1 s.
001b = 1 s – 2 s.
010b = 2 s – 4 s.
011b = 4 s – 8 s.
100b = 8 s – 16 s.
101b = 16 s – 32 s.
110b = 32 s – 64 s.
111b = No limit.
These bits configure the initial hardware value of the PCI configuration,
Device CAP, and Endpoint L1 Acceptable Latency registers following power
up.
L0s acceptable latency for the configuration space
Default = (512 ns).
Defined encoding:
000b = Less than 64 ns.
001b = 64 ns – 128 ns.
010b = 128 ns – 256 ns.
011b = 256 ns – 512 ns.
100b = 512 ns – 1 s.
101b = 1 s – 2 s.
110b = 2 s – 4 s.
111b = No limit.
These bits configure the initial hardware value of the PCI configuration,
Device CAP, and Endpoint L0s Acceptable Latency registers following
power up.
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