82598EB Datasheet, PDF (582/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Connecting the JTAG Port
8.15 Connecting the JTAG Port
The 82598 10 Gigabit Ethernet Controller contains a test access port (3.3 V dc only) conforming to the
IEEE 1149.1a-1994 (JTAG) Boundary Scan specification. To use the test access port, connect these
balls to pads accessible by your test equipment.
For proper operation a pull-down resistor should be connected to the JTCK and JRST_N signals and pull
up resistors to the JTMS and JTDI signals.
A BSDL (Boundary Scan Definition Language) file describing the 82598 10 Gigabit Ethernet Controller
device is available for use in your test environment. The controller also contains an XOR test tree
mechanism for simple board tests. Details of XOR tree operation are available from your Intel
representative.
8.16 Thermal Design Considerations
In a system environment, the temperature of a component is a function of both the system and
component thermal characteristics. System-level thermal constraints consist of the local ambient
temperature at the component, the airflow over the component and surrounding board, and the
physical constraints at, above, and surrounding the component that may limit the size of a thermal
enhancement (heat sink).
The component's case/die temperature depends on:
• Component power dissipation
• Size
• Packaging materials (effective thermal conductivity)
• Type of interconnection to the substrate and motherboard
• Presence of a thermal cooling solution
• Power density of the substrate, nearby components, and motherboard
All of these parameters are pushed by the continued trend of technology to increase performance levels
(higher operating speeds, MHz) and power density (more transistors). As operating frequencies
increase and packaging size decreases, the power density increases and the thermal cooling solution
space and airflow become more constrained. The result is an increased emphasis on system design to
ensure that thermal design requirements are met for each component in the system.
8.16.1 Importance of Thermal Management
The thermal management objective is to ensure system component temperatures are maintained in
functional limits. The functional temperature limit is the range in which electrical circuits meet specified
performance requirements. Operation outside the functional limit can degrade performance, cause logic
errors, or cause system damage.
Temperatures exceeding the maximum operating limits may result in irreversible changes in the device
operating characteristics. Note that sustained operation at component maximum temperature limit may
affect long-term device reliability.
8.16.2 Packaging Terminology
The following is a list of packaging terminology used in this document.
FCBGA Flip Chip Ball Grid Array: A surface-mount package using a combination of flip chip and BGA
structure whose PCB-interconnect method consists of Pb-free solder ball array on the interconnect side
of the package. The die is flipped and connected to an organic build-up substrate with C4 bumps.
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