82598EB Datasheet, PDF (63/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
3.1.1.5.2 Transmitted Messages
The transaction layer is also responsible for transmitting specific messages to report internal/external
events (such as interrupts and PMEs).
Table 3-5. Initiated Messages
Message
code [7:0]
Routing
r2r1r0
0x20
100b
0x21
100b
0x22
100b
0x23
100b
0x24
100b
0x25
100b
0x26
100b
0x27
100b
0x30
000b
0x31
000b
0x33
000b
0x18
000b
0x1B
101b
Assert INT A
Assert INT B
Assert INT C
Assert INT D
DE- Assert INT A
DE- Assert INT B
DE- Assert INT C
DE- Assert INT D
ERR_COR
ERR_NONFATAL
ERR_FATAL
PM_PME
PME_TO_Ack
Message
3.1.1.6 Ordering Rules
The 82598 meets the PCIe ordering rules (PCI-X rules) by following the simple device model:
1. Deadlock Avoidance – Master and target accesses are independent – The response to a target
access does not depend on the status of a master request to the bus. If master requests are
blocked (due to no credits), target completions can still proceed (if credits are available).
2. Descriptor/Data Ordering – the device does not proceed with some internal actions until respective
data writes have ended on the PCIe link:
3. The 82598 does not update an internal header pointer until the descriptors that the header pointer
relates to are written to the PCIe link.
4. The 82598 does not issue a descriptor write until the data that the descriptor relates to is written to
the PCIe link.
5. The 82598 might issue the following master read request from each of the following clients:
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