82598EB Datasheet, PDF (54/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
The common base protocol uses split transactions along with several mechanisms to eliminate wait
states and to optimize re-ordering transactions to improve system performance.
3.1.1.1 Architecture, Transaction and Link Layer Properties
• Split transaction, packet-based protocol
• Common flat address space for load/store access (for example, PCI addressing model):
—32-bit memory address space to enable a compact packet header (must be used to access
addresses below 4 Gb)
—64-bit memory address space using an extended packet header
• Transaction layer mechanisms:
—PCI-X style relaxed ordering
—Optimizations for no-snoop transactions
• Credit-based flow control
• Packet sizes/formats:
—Maximum packet size supports 128-byte and 256-byte data payload
—Maximum read request size: 256 bytes
• Reset/initialization:
—Frequency/width/profile negotiation performed by hardware
• Data integrity support:
—Using CRC-32 for Transaction layer Packets (TLP)
• Link Layer Retry (LLR) for recovery following error detection:
—Using CRC-16 for Link Layer (LL) messages
• No retry following error detection:
—8b/10b encoding with running disparity
• Software configuration mechanism:
—Uses PCI configuration and bus enumeration model
— PCIe-specific configuration registers mapped via PCI extended capability mechanism
• Baseline messaging:
—In-band messaging of formerly side-band legacy signals (Interrupts, etc.)
—System-level power management supported via messages
• Power management:
—Full support for PCIm
—Wake capability from D3cold state
—Compliant with ACPI, PCIm software model
—Active state power management
• Support for PCIe v2.0 (2.5GT/s):
—Support for completion time out
—Support for additional registers in the PCIe capability structure
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