82598EB Datasheet, PDF (126/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Up
Table 3-36. Timing Parameters
Parameter
t_xog
t_ppg
t_ee
tpgtrn
tpgres
Description
Xosc stable from power stable
Internal power good delay from
valid power rail
EEPROM read duration
PCIe PWRGD to start of link
training
External PWRGD to response to
first configuration cycle
Min
Max.
10 ms
35 ms 35 ms
Notes
20 ms
20 ms According to PCIe spec
1s
According to PCIe spec
3.2.1.3 Reset Operation
The 82598 reset sources are as follows:
• LAN_PWR_GOOD or Internal Power On Reset – The 82598 has an internal mechanism for sensing
the power pins. Once the power is up, a stable 82598 creates an internal reset, this reset acts as
a master reset of the entire 82598. It is level sensitive, and while it is 0b, holds all registers in
reset. LAN_PWR_GOOD or internal power on reset is interpreted as an indication that the 82598
power supplies are all stable. Note that LAN_PWR_GOOD or internal power on reset changes
state during system power-up.
• PE_RST_N – Asserting PE_RST_N indicates that both the power and the PCIe clock sources are
stable. This pin also asserts an internal reset after a D3cold exit. Most units are reset on the rising
edge of PE_RST_N. The only exception is the GIO unit, which is kept in reset while PE_RST_N is
de-asserted (level).
• In-band PCIe reset – The 82598 generates an internal reset in response to a PHY message from
the PCIe or when the PCIe link goes down (entry to polling or detect state). This reset is
equivalent to PCI reset in previous (PCI) GbE controllers.
• D3hot to D0 transition – This is also known as ACPI Reset. The 82598 generates an internal reset
on the transition from D3hot power state to D0 (caused after configuration writes from D3 to D0
power state). Note that this reset is per function and resets only the function that transitioned
from D3hot to D0.
• Software Reset – Software can reset the 82598 by writing the Device Reset bit of the Device
Control Register (CTRL.RST). The 82598 re-reads the per-function EEPROM fields after software
reset. Bits that are normally read from the EEPROM are reset to their default hardware values.
Note that this reset is per function and resets only the function that received the software reset.
PCI Configuration space (configuration and mapping) of the 82598 is unaffected. Prior to issuing
a software reset, the software device driver needs to execute the master disable algorithm.
• Link Reset – Software can reset the 82598 MAC by writing the Link Reset bit of the Device Control
Register (CTRL.LRST). The 82598 re-reads the per-function EEPROM fields after link reset. Bits
that are normally read from the EEPROM are reset to their default hardware values. Note that this
reset is per function and resets only the function that received the link reset. Note that the 82598
executes a software reset each time link reset is asserted. Link reset can also be referred as MAC
reset. Prior to issuing link reset, the software device driver needs to execute the master disable
algorithm.
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