82598EB Datasheet, PDF (288/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Undefined I/O Offsets
4.3.3 Undefined I/O Offsets
I/O offsets 0x08 through 0x1F are considered to be reserved offsets with the I/O window. Dword reads
from these addresses returns 0xFFFF; writes are discarded.
4.4
Device Registers
4.4.1 Terminology
Shorthand
Description
R/W
Read/Write. A register with this attribute can be read and written. If written since reset, the value read reflects
the value written.
R/W S
Read/Write Status. A register with this attribute can be read and written. This bit represents status of some
sort, so the value read may not reflect the value written.
RO
Read Only. If a register is read only, writes to this register have no effect.
WO
Write Only. Reading this register may not return a meaningful value.
R/WC
Read/Write Clear. A register bit with this attribute can be read and written. However, a Write of a 1b clears
(sets to 0b) the corresponding bit and a write of a 0b has no effect.
R/Clr
Read Clear. A register bit with this attribute is cleared after read. Writes have no effect on the bit value.
R/W SC
Read/Write Self Clearing. When written to a 1b the bit causes an action to be initiated. Once the action is
complete, the bit returns to 0b.
RO/LH
Read Only, Latch High. The bit records an event or the occurrence of a condition to be recorded. When the
event occurs the bit is set to 1b. After the bit is read, it returns to 0b unless the event is still occurring.
RO/LL
Read Only, Latch Low. The bit records an event. When the event occurs the bit is set to 0b. After the bit is read,
it reflects the current status.
RW0
Ignore Read, Write Zero. The bit is a reserved bit. Any values read should be ignored. When writing to this bit
always write a 0b.
RWP
Ignore Read, Write Preserving. This bit is a reserved bit. Any values read should be ignored. However, they
must be saved. When writing the register the value read out must be written back. (There are currently no bits
that have this definition.)
4.4.2 Register List
The 82598's non-PCIe configuration registers are listed in Table 4-3. These registers are ordered by
group and are not necessarily listed in the order that they appear in address space.
All registers should be accessed as a 32-bit width on reads with an appropriate software mask.
Software read/modify/write mechanism should be invoked for partial writes.
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