82598EB Datasheet, PDF (173/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Hardware EEPROM Sections
5:3
L0s_Se_Ext_Latency
110b
2:0
L0s_Co_Ext_Latency
110b
L0s exit latency for active state power management (separated reference
clock) – (latency between 2 μs – 4 μs).
Defined encoding:
000b = Less than 64 ns.
001b = 64 ns – 128 ns.
010b = 128 ns – 256 ns.
011b = 256 ns – 512 ns.
100b = 512 ns – 1 s.
101b = 1 s – 2 s.
110b = 2 s – 4 s.
111b = More than 4 s.
These bits configure the initial hardware value of the PCI configuration,
Link CAP, and L0s Exit Latency registers (when working with a separate
clock) following power up.
L0s exit latency for active state power management (common reference
clock) – (latency between 2 μs – 4 μs).
Defined encoding:
000b = Less than 64 ns.
001b = 64 ns – 128 ns.
010b = 128 ns – 256 ns.
011b = 256 ns – 512 ns.
100b = 512 ns – 1 s.
101b = 1 s – 2 s.
110b = 2 s – 4 s.
111b = More than 4 s.
These bits configure the initial hardware value of the PCI configuration,
Link CAP, and L0s Exit Latency registers (when working with a common
clock) following power up.
3.4.3.3.3 PCIe Init Configuration 2 – Offset 2
Bit
15:12
11:8
Name
Reserved
Extra NFTS
7:0
NFTS
Default
0b
0x7
0xB0
Description
Reserved.
Extra Number of Fast Training Signal (NFTS) that is added to the original
requested number of NFTS (as requested by the upstream component).
Number of special sequences for L0s transition to L0. The 82598 requires
at least 0xB0 NFTS for proper functionality.
3.4.3.3.4 PCIe Init Configuration 3 – Offset 3
Bit
15
Name
Master_Enable
14
Scram_dis
Default
0b
0b
Description
When set to 1b, this bit enables the PHY to be a master (upstream component/
cross link functionality).
Scrambling Disable
When set to 1b, this bit disables PCIe LFSR scrambling.
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