82598EB Datasheet, PDF (404/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.13.18MAC Address High and Max Frame Size – MHADD (0x04268; RW)
Field
ReservedMACH
MFS
Bit(s)
15:0
Initial
Value
Description
0x0
Reserved
MAC ADRESS [47:32] Most significant 16 bits of the MAC
address
31:16
0x5EE
MAX Frame Size
Maximum number of bytes in a frame that can be
transmitted. Sets the boundary between oversize and
jumbo frames on receive when jumbo frames are enabled.
The value includes the CRC.
Note: For the receive side, if the packet has a VLAN field
then the value of the MFS is internally increased by four
bytes.
Note: For the transmit side, enforcing the MAX frame size
restriction should be done by software (the 82598 does not
limit the transmit packet size).
4.4.3.13.19XGXS Status 1 – PCSS1 (0x4288; RO)
Field
Reserved
Local fault
Reserved
PCS receive
link status
Reserved
Bit(s)
Initial
Value
Description
31:8
0x0
Reserved
7
1b
1b = LF detected on transmit or receive path.
The LF bit is set to 1b when either of the local fault bits located in PCS Status 2
register are set to 1b.
0b = No LF detected on receive path.
6:3
0x0
Reserved
2
0b
1b = PCS receive link up.
For 10BASE-X ->lanes de-skewed.
0b = PCS receive link down.
The receive link status remains cleared until it is read (latching low).
1:0
00b
Reserved
4.4.3.13.20XGXS Status 2 – PCSS2 (0x0428C; RO)
Field
Reserved
Bit(s)
Initial
Value
31:16
0x0
Reserved
Description
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