82598EB Datasheet, PDF (220/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Receive Functionality
• VP (bit 3) – Packet is 802.1q (matched VET); indicates strip VLAN in 802.1q packet
• Reserved (bit 2) – Reserved
• EOP (bit 1) – End of packet
• DD (bit 0) – Descriptor done
EOP, DD
Packets that exceed the receive buffer size span multiple receive buffers. EOP indicates whether this is
the last buffer for an incoming packet. DD indicates whether hardware is done with the descriptor.
When set along with EOP, the received packet is complete in main memory. Software can determine
buffer usage by setting the status byte to zero before making the descriptor available to hardware, and
checking it for non-zero content at a later time. For multi-descriptor packets, packet status is provided
in the final descriptor of the packet (EOP set). If EOP is not set for a descriptor, only the Address,
Length, and DD bits are valid.
VP
The VP field indicates whether the incoming packet's type matches VET (if the packet is a VLAN
(802.1q) type). It's set if the packet type matches VET and VLNCTRL.VME is set. It also indicates that
VLAN has been stripped in the 802.1q packet. For a further description of 802.1q VLANs please see
Section 3.5.5.
IPCS, L4CS, UDPCS: The meaning of these bits is shown in the following table:
L4CS
0b
UDPCS
0b
IPCS
0b
1b
0b
1b/0b
1b
1b
1b/0b
Functionality
Hardware does not provide checksum offload.
Special case: hardware does not provide UDP checksum offload for IPv4 packet with
UDP checksum = 0b.
Hardware provides IPv4 checksum offload if IPCS active and TCP checksum offload.
Pass/Fail indication is provided in the Error field – IPE and TCPE. See PKTTYPE table
for supported packet types.
Hardware provides IPv4 checksum offload if IPCS is active along with UDP checksum
offload. Pass/fail indication is provided in the Error field – IPE and TCPE. See
PKTTYPE table for supported packet types.
See Section 3.5.2.12 for a description of supported packet types for receive checksum offloading. IPv6
packets do not have the IPCS bit set, but might have the L4CS bit set if the 82598 recognized the TCP
or UDP packet.
PIF
Hardware supplies the PIF field to expedite software processing of packets. Software must examine any
packet with PIF set to determine whether to accept the packet. If PIF is clear, then the packet is known
to be for this station, so software need not look at the packet contents. Packets passing only the
Multicast Vector (MTA) but not any of the MAC address exact filters (RAH, RAL) has PIF set.
Error Field (8 bit offset 40)
Most error information appears only when the SBP bit (FCTRL.SBP) is set and a bad packet is received.
Refer to Table 3-51 for a definition of the possible errors and their bit positions.
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