82598EB Datasheet, PDF (31/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Test Interface Signals
DEV_PWRDN_N
B13
O
LAN0_DIS_N
B14
T/s
AUX_PWR
B16
T/s
LAN_PWR_GOOD
B17
In
This pin can control the external power supply to the 82598 according to
the internal power state using an external circuitry.
This pin is a strapping pin latched at the rising edge of LAN_PWR_GOOD,
Internal Power On Reset, PE_RST_N, or in-band PCIe reset. If this pin is
not connected or driven high during initialization, LAN 0 is enabled. If this
pin is driven low during initialization, LAN 0 port is disabled.
Auxiliary Power Available. When set, indicates that auxiliary power is
available and the 82598 should support D3_COLD power state if enabled to
do so. This pin is latched at the rising edge of Internal Power On Reset or
LAN_PWR_GOOD.
LAN_PWR_GOOD. A transition from low to high initializes the 82598 by
resetting it. This pin is used in conjunction with POR_BYPASS. For the pin to
operate correctly, the LAN_PWR_GOOD circuit needs to be bypassed
(POR_BYPASS = 1b).
2.10 Test Interface Signals
Table 2-13. Test Interface Signals
Symbol
JTCK
JTDI
JTDO
JTMS
JRST_N
Pin
Number
Type
F2
In
D2
In
F1
O/d
E2
In
C2
In
Name and Function
JTAG Clock Input.
JTAG Data Input.
JTAG Data Output.
JTAG TMS Input.
JTAG Reset Input. Active low reset for the JTAG port.
2.11 Power Supplies
Table 2-14. Digital and Analog Supplies
Symbol
VCC3P3
Pin Number
AB1, V1, N1, H1, C1.
Type
Name and
Function
3.3 V dc
3.3 V dc
Power Input.
31